Generally, memory chips comprise an array of memory cells interconnected by bit lines and word lines. The word lines and bit lines are used to read and write binary values to each of the memory cells, wherein each memory cell represents a bit of information. Because each memory cell represents a bit of information and may be connected to other circuitry, it is desirable that the electrical and operational characteristics of all memory cells be consistent.
The operational and electrical characteristics of memory cells, however, vary depending on where a memory cell is located within the layout of the memory array. For example, memory cells along the edge of the memory array may have different electrical and operational characteristics than memory cells located in the inner region of the memory array. One cause of this difference in the electrical and operational characteristics is the lithography process. Generally, a lithography process involves patterning a mask layer on an underlying layer, and then performing a process such as implanting or etching the underlying layer. The density of the structures during this lithography process, however, is different for the region containing the inner memory cell and the region of the edge memory cell. It has been found that this difference in density may affect some processes such as the etching rates and implantation concentration, thereby causing a difference in the electrical and operational characteristics between memory cells located near or along the edge (e.g., sparsely populated regions) and memory cells located in the inner regions of the memory array (e.g., densely populated regions).
Another cause is the well-proximity effect. Implant masks, such as a patterned photo-resist layer, are used during the formation of wells. During the implantation process, some of the ions may scatter out of the edge of the implant mask and implant in the surface of the silicon near the mask edge. The implanted ions near the mask edge may alter the threshold voltage of those devices formed in the well. Because the distances between a device and a neighboring well may vary, the performance and operational characteristics of memory cells in the inner region of the memory array may be different than memory cells along the edge of the memory array.
Yet another cause of the different operating characteristics between inner memory cells and edge memory cells is the stress that may be induced by shallow-trench isolations (STIs). STIs are typically formed by etching a trench in the substrate and filling the trench with a dielectric material, typically a high-density oxide. The STIs, however, may exert a tensile or compressive stress in the channel region of nearby transistors, thereby altering the operational and electrical characteristics such as the threshold voltage and on/off current levels of the nearby transistors. This difference is particularly noticeable with transistors in memory cells along the edge of the memory array.
Therefore, there is a need for a memory array such that the electrical and operational characteristics of semiconductor devices are more consistent throughout the chip.